Design, Implementation and Performance Comparison of Different Branch Predictors on Pipelined-CPU

Abstract

Branch predictors are implemented on pipelined CPUs having different types of instructions. Both unconditional and conditional branches are implemented utilizing different instruction set formats of the CPU. A basic pipelined CPU consists of three stages Fetch, Decode, and Execute. All the instructions are executed in parallel, hence every stage is busy with an instruction which saves the wastage of time and increases the performance. Hazards will occur because of Conditional branches in the pipeline which changes the sequential flow of execution. To overcome these hazards, the pipeline should be made empty and loaded with appropriate instruction which avoids the wastage of time. Hence Branch predictors are essential in CPUs as it saves the wastage of time by guessing the correct sequence of instruction as the conditional branches changes the sequence of instructions. Three types of Branch Predictors are implemented on pipelined CPUs separately which are simulated, synthesized and bit-files are generated using Xilinx ISE tool, the bit-files are later dumped on Xilinx SPARTAN-6 board and the results are analyzed using CHIPSCOPE.