{"title":"2.5 Gb/s 8/spl times/8 self-routing switch GaAs LSIs for ATM switching systems","authors":"H. Yamada, M. Tunotani, F. Kaneyama, S. Seki","doi":"10.1109/GAAS.1994.636922","DOIUrl":null,"url":null,"abstract":"2.5 Gb/s 8/spl times/8 self-routing switch LSIs have been developed for the asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. This switching system consists of three LSIs using a 0.5 /spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells, a \"NEMAWASHI\" network LSI for previously detecting the cells with the same output port address, and a demultiplexer LSI for converting the cells from the switching network into the eight streams per a channel. These LSIs are mounted in a 520 pin multi-chip module package. The number of total logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and the throughput is 20.8 Gb/s.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1994.636922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
2.5 Gb/s 8/spl times/8 self-routing switch LSIs have been developed for the asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. This switching system consists of three LSIs using a 0.5 /spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells, a "NEMAWASHI" network LSI for previously detecting the cells with the same output port address, and a demultiplexer LSI for converting the cells from the switching network into the eight streams per a channel. These LSIs are mounted in a 520 pin multi-chip module package. The number of total logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and the throughput is 20.8 Gb/s.