Concurrent Architecture of High Speed Viterbi Decoder Using Xilinx HLS Tool

Abstract

Viterbi decoder finds its applications in different areas like radio communication, satellite communication, hard disk drives and automatic speech recognitions. The general building blocks implementing the Viterbi decoder are the Branch Metric Unit, Path Metric Unit and Traceback Unit. Viterbi decoder becomes possible because it uses maximum likelihood decoding to interpret the coded message, but, on the other hand, is considered to be the high resource consuming block. To address this issue, in the proposed research work, concurrent architecture of the Viterbi decoder is proposed. The architecture is described using hardware description language and it is targeted to the Kintex series Field Programmable Gate Arrays (FPGA) which are fabricated at 28nm technology. For describing the architecture Xilinx Vivado High Level Synthesis (HLS) tool is preferred. The outcome of the proposed architecture is evaluated using different ascendency parameters like time, frequency, power utilization and resource utilization.