Hardware characterization of Integer-Net based seizure detection models on FPGA

Abstract

Deployment of deep neural network (DNN) infer-ence on platforms like field programmable gate array (FPGA) for acceleration can be challenging because of the limited resource availability and a large number of floating-point matrix operations involved. Therefore, in this work a hardware efficient algorithm called Integer-Net which is based on approximate floating-point operations is studied for edge DNN inference deployment. This algorithm uses integerized floating-point arithmetic with a scalar correction for the matrix operations. Electroencephalo-gram (EEG) signal based automatic high-speed epileptic seizure detection using Integer-Net convolutional neural network (CNN) was hardware-implemented on Zynq-7000 SoC to characterize performance efficiency and hardware resources utilized against the full precision model. Implementation was benefited by the accelerated outputs, leveraged the optimum on-board resources, and at the same time with the help of configurable integer bit-width, facilitated keeping the accuracy close to the original model. This is the first time, Integer-Net based designs and their novel hybrid versions were employed and investigated for the hardware acceleration of a CNN network for seizure detection on FPG A. A latency acceleration of 5.65x with the on-chip memory usage reduction factor of 5.99x was achieved by the optimized hybrid integerized CNN model.