Minimising Impact of Local Congestion in Networks-on-Chip Performance by Predicting Buffer Utilisation

Aqib Javed, J. Harkin, L. McDaid, Junxiu Liu
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引用次数: 2

Abstract

Networks-on-Chip (NoC) were designed to enhance the communication performance of Multi-processor Systems-on-Chip (MPSoC). NoCs are equipped with buffered input channels which queue incoming data and minimise routing stress especially under uneven traffic distributions. Buffer utilization of a router node provides an early indication to potential local congestion. In this work we propose a novel Spiking Neural Network (SNN) based congestion prediction model to predict input buffer utilization as a congestion parameter to minimize impact of potential local congestion. Router-level and Network-level models are proposed in predicting congestion at each NoC router node. Results show that the router and network models can predict buffer utilization patterns with an average accuracy of 91.89% and 93.76%, respectively.
通过预测缓冲区利用率最小化局部拥塞对片上网络性能的影响
片上网络(NoC)旨在提高多处理器片上系统(MPSoC)的通信性能。noc配备了缓冲输入通道,对传入数据进行排队,并将路由压力降至最低,特别是在流量分布不均匀的情况下。路由器节点的缓冲区利用率为潜在的本地拥塞提供了早期指示。在这项工作中,我们提出了一种新的基于峰值神经网络(SNN)的拥塞预测模型,以预测输入缓冲区利用率作为拥塞参数,以最小化潜在的局部拥塞影响。提出了路由器级和网络级模型来预测每个NoC路由器节点的拥塞。结果表明,路由器和网络模型预测缓冲区利用模式的平均准确率分别为91.89%和93.76%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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