ESD: design for IC chip quality and reliability

Abstract

ESD is a major concern for IC chip quality both from building-in-reliability requirement and from long-term field operation requirement. The damage phenomena, either from human handling or machine contact, could appear as thermal damage and oxide rupture. In this paper, the IC damage phenomena due to ESD, the effects on the IC functionality, the proper methods to overcome these with on-chip protection designs, and the challenges facing these protection methods with the advanced process and package technologies are presented. Simulation and modeling methods that are currently used to improve the protection designs are also reviewed.