Machine Learning Techniques for the Energy and Performance Improvement in Network-on-Chip (NoC)

Abstract

On resource-constrained embedded devices (e.g., Internet of Things nodes), deep neural network inference requires specialized architectural solutions to deliver the greatest possible performance, energy, and cost trade-offs. In this regard, a Network-on-Chip architecture with many parallel and specialized cores is one of the most promising (NoC). An architecture parameter that impacts deep neural networks' performance is the number and size of memory interfaces. Using these and other architectural criteria, we investigate the design space that can be created. We demonstrate how on-chip communication dominates delay while memory consumes the majority of energy. According to the findings, a new research area devoted to improving the performance and energy efficiency of on-chip communication fabrics and memory subsystems should be estavlished.