Impact of Process Variation Induced Transistor Mismatch on Sense Amplifier Performance

Abstract

Sense amplifier is a very critical peripheral circuit in memories as its performance strongly affects both memory access time, and overall memory power dissipation. As the device dimensions scale below 100nm, the process variations are increasing and are impacting the circuit design significantly. The circuit yield loss caused by the process and device parameter variation has been more pronounced than before [1]. In this paper, effects of process variation induced transistor mismatch on sense amplifier performance are studied. A comparative study of the effect of mismatch on delay and yield for different sense amplifier configurations at 90 nm technology is presented.