A D-Type Flip-Flop with Enhanced Timing Using Low Supply Voltage

Abstract

This work proposes a novel master-slave latch D-type Flip-Flop. It consists of a reset-set slave latch and an asymmetrical single data input master latch. By reducing the number of stages and removing signal conditioning circuitry in the master latch, setup time has been significantly reduced and power consumption has improved. The proposed flip-flop is competitive to other state of the art low power flip-flops in addition to the conventional Transmission Gate Flip-flop (TGFF) in terms of performance, power consumption and area. In simulations, the proposed flip-flop has achieved up to 71.5% improvement in setup time, 36.5% improvement in D-Q delay time and up to 56.5% less power delay product (PDP) with 10% data activity compared to Topologically Compressed Flip-Flop (TCFF), which is a low power flip-flop. Further, it has achieved 11% smaller circuit area compared with TGFF. This work includes the proposed flip-flop's circuit schematic, layout design and simulations using Hspice tool with 28nm CMOS technology and a 1V supply voltage at 1 GHz clock (CLK).