Neural Network Compiler for Parallel High-Throughput Simulation of Digital Circuits

Ignacio Gavier, Joshua Russell, Devdhar Patel, E. Rietman, H. Siegelmann
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Abstract

Register Transfer Level (RTL) simulation and verification of Digital Circuits are extremely important and costly tasks in the Integrated Circuits industry. While some simulators have incorporated the exploitation of parallelism in the structure of Digital Circuits to run on multi-core CPUs, the maximum throughput they achieve quickly reaches a plateau, as described by Amdahl’s Law. Recent research from Nvidia has obtained much higher throughput in simulations using GPUs, highlighting the potential of these devices for Digital Circuit simulation. However, they were required to incorporate sophisticated algorithms to support GPU simulation. In addition, the unbalanced structure of real-life Digital Circuits provides difficulties for processing on multi-threaded devices. In this paper, we present a Digital Circuit compiler that utilizes Neural Networks to exploit the various parallelisms in RTL simulation, making use of PyTorch, a widely-used Neural Network framework that facilitate their simulation on GPUs. By using properties of Boolean Functions, we developed a novel algorithm that converts any Digital Circuit into a Neural Network, and optimization techniques that help in pushing the thread computational capability to the limit. The results show three orders of magnitude higher throughput than Verilator RTL simulator, an improvement of one order of magnitude compared to the state-of-the-art GPU techniques from Nvidia. We believe that the use of Neural Networks not only provides a significant improvement in simulation and verification tasks in the Integrated Circuits industry, but also opens a line of research for simulators at the logic and physical gate level.
并行高通量数字电路仿真的神经网络编译器
数字电路的寄存器传输电平(RTL)仿真与验证是集成电路行业中极其重要且昂贵的任务。虽然一些模拟器已经在数字电路结构中利用并行性在多核cpu上运行,但它们实现的最大吞吐量很快达到了一个平台,正如Amdahl定律所描述的那样。Nvidia最近的研究已经在使用gpu的模拟中获得了更高的吞吐量,突出了这些设备在数字电路模拟中的潜力。然而,他们需要结合复杂的算法来支持GPU模拟。此外,现实数字电路的不平衡结构为多线程设备的处理提供了困难。在本文中,我们提出了一个数字电路编译器,它利用神经网络来利用RTL仿真中的各种并行性,利用PyTorch,一个广泛使用的神经网络框架,促进它们在gpu上的仿真。通过使用布尔函数的特性,我们开发了一种将任何数字电路转换为神经网络的新算法,以及有助于将线程计算能力推向极限的优化技术。结果显示,与Verilator RTL模拟器相比,吞吐量提高了三个数量级,与Nvidia最先进的GPU技术相比,提高了一个数量级。我们相信,神经网络的使用不仅为集成电路行业的仿真和验证任务提供了重大改进,而且还为逻辑和物理栅极级的模拟器开辟了一系列研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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