Data flow chip ImPP and its system for image processing

ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing Pub Date : 1986-04-07 DOI:10.1109/ICASSP.1986.1169141

M. Iwashita, T. Temma

{"title":"Data flow chip ImPP and its system for image processing","authors":"M. Iwashita, T. Temma","doi":"10.1109/ICASSP.1986.1169141","DOIUrl":null,"url":null,"abstract":"A data flow image pipelined processor VLSI chip (ImPP:µPD7281) has been developed. Its hardware architecture and the experimental Template Controlled Image Processing System -3 (TIP-3), which includes 8 ImPP chips, are described. The ImPP is characterized by its data flow architecture and flexible pipeline processing. The ImPP has a uni-directional pipeline bus. The connection between ImPPs is easy and does not require extra circuits. The processing performance can be increased by connecting many chips to each other. In this multiple ImPP configuration, individual ImPPs share different portions of the pipeline programs and different portions of spatial data. The ImPP can be used in various system configurations. A single ImPP chip is sufficient for simple processing and multiple ImPPs are useful for a faster image processing system. Performance estimation using a software simulator, and also using an actual hardware system has been carried out. TIP-3's top performance is 40 MIPS. The main factors which influence execution efficiency are discussed and analyzed.","PeriodicalId":242072,"journal":{"name":"ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1986-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASSP.1986.1169141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

Abstract

A data flow image pipelined processor VLSI chip (ImPP:µPD7281) has been developed. Its hardware architecture and the experimental Template Controlled Image Processing System -3 (TIP-3), which includes 8 ImPP chips, are described. The ImPP is characterized by its data flow architecture and flexible pipeline processing. The ImPP has a uni-directional pipeline bus. The connection between ImPPs is easy and does not require extra circuits. The processing performance can be increased by connecting many chips to each other. In this multiple ImPP configuration, individual ImPPs share different portions of the pipeline programs and different portions of spatial data. The ImPP can be used in various system configurations. A single ImPP chip is sufficient for simple processing and multiple ImPPs are useful for a faster image processing system. Performance estimation using a software simulator, and also using an actual hardware system has been carried out. TIP-3's top performance is 40 MIPS. The main factors which influence execution efficiency are discussed and analyzed.

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数据流芯片ImPP及其图像处理系统

开发了一种数据流图像流水线处理器VLSI芯片(ImPP:µPD7281)。介绍了其硬件结构和包含8个ImPP芯片的实验性模板控制图像处理系统-3 (TIP-3)。ImPP的特点是数据流架构和灵活的流水线处理。ImPP具有单向管道总线。impp之间的连接很容易，不需要额外的电路。通过将多个芯片相互连接，可以提高处理性能。在这种多ImPP配置中，各个ImPP共享管道程序的不同部分和空间数据的不同部分。ImPP可用于各种系统配置。单个ImPP芯片足以进行简单的处理，多个ImPP芯片可用于更快的图像处理系统。利用软件模拟器和实际硬件系统进行了性能评估。TIP-3的最高性能为40 MIPS。对影响执行效率的主要因素进行了讨论和分析。

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ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing

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