Design and Analysis of 8-bit ripple Carry Adder using nine Transistor Full Adder

G. Padmini, O. Rajesh, K. Raghu, N. Sree, C. Apurva, K. Saikumar
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引用次数: 19

Abstract

This paper uses a nine-transistor full adder model to design an eight-bit ripple carry adder for less power consumption. The conventional full adder design consists of 28 transistors which constitute high power consumption. Decreasing the transistor count decreases the power consumption in the circuit. A single bit full adder using a nine-transistor is implemented and using this adder, an eight-bit ripple carries adder is designed. A conventional CMOS adder, both single bit and 8-bit ripple carry adder remain also designed to compare the power outputs. Microwind-2.6a and DSCH 2.6 are used to acquire the power outputs of each circuit. To conclude, power comparisons for both single and eight-bit adders using the 9-transistor and conventional CMOS models are made.
采用9晶体管全加法器的8位纹波进位加法器的设计与分析
本文采用9晶体管全加法器模型设计了一个8位纹波进位加法器,以降低功耗。传统的全加法器设计由28个晶体管组成,功耗很高。减少晶体管数量可以降低电路的功耗。实现了一个采用9晶体管的单位全加法器,并利用该加法器设计了一个8位纹波加法器。传统的CMOS加法器,包括单比特和8比特纹波进位加法器,也被设计用来比较功率输出。采用Microwind-2.6a和DSCH 2.6采集各电路的输出功率。最后,对使用9晶体管和传统CMOS模型的单位加法器和8位加法器的功率进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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