SEU mitigation of rad-tolerant Xilinx FPGA using external scrubbing for geostationary mission

Abstract

This paper presents the design and implementation of an effective SEU mitigation technique for rad-tolerant Xilinx virtex-4 xqr4vsx55 FPGA used in implementation of Digital Bandwidth Efficient Filter (DBEF) subsystem for INSAT-3DR payload. The Single Event Effects (SEE) on the virtex-4 FPGA are minimized using an external scrubbing engine which is implemented using rad-hard RTSX32SU-CQ84 Actel FPGA. The availability and reliability analysis shows an optimum window for performing scrubbing function in Geo-stationary earth orbit.