Noise Tolerant Techniques in Dynamic CMOS Logic Style: A Review Paper

Abstract

Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino logic (dynamic logic with an inverter at the output) also faces this problem. This paper consists of an overview of various noise tolerant techniques for dynamic logic explaining their functioning and reliability for comb acting noise.