FPGA Implementation for LDPC Decoders Using A Novel Memory Effective Decoding Algorithm

Abstract

In this paper, a novel memory effective algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity and hardware resources. The algorithm, called check node self-update (CNSU) algorithm, is based on layered normalized min-sum (LNMS) decoding algorithm while utilizing iteration parallel techniques to integrate both variable nodes (VNs) message and a-posterior probability message into the check nodes (CNs) message, which eliminates memories of both the variable node and the a-posterior probability message as well as updating module of a-posterior probability message in CNs unit. Based on the proposed CNSU algorithm, design of partially parallel decoder architecture and serial simulations followed by implementation on the Stratix II EP2S180 FPGA are presented. The results show that the proposed algorithm significantly reduces hardware memory resources and chip area while keeping the benefit of bit-error-rate (BER) performance and speeding up of convergence with LNMS.