Design Procedure for a Folded-Cascode and Class AB Two-Stage CMOS Operational Amplifier

Abstract

This paper presents a low-noise two-stage operation amplifier design procedure based on standard CMOS process. Unlike the previous researches that depict the design flow based on some simple circuit topologies for simplicity, this paper adopts the folded cascade input and Class AB output two-stage operational amplifier that is more admitted by academia and widely used into industry. This presented procedure begins with the key noise requirement to firstly determine the input difference pair whose transconductance is the most important parameter related to other electrical characters. Then the expressions and relationships of other parameters (such as slew rate, bandwidth, gain, phase margin, power consumption and signal swing) are derived under the constraint of noise requirement. Besides that, all sizes of devices are confirmed considering chip area, matching relation and layout. The low noise amplifier under the guidance of this proposed design procedure is implemented on a standard 0.18μm CMOS process. The measured results and simulation are closed agree with the expect results. So this design procedure offers designers an efficient way from electrical characters to key devices sizes based on the common operation amplifier circuit.