Performance enhancement of encryption and authentication IP cores for IPSec based on multiple-core architecture and dynamic partial reconfiguration on FPGA

Abstract

In this paper, we propose a Multiple Core architecture and an DMA bus connectivity to increase the processing speed of encryption and authentication cores in high speed IPSec security systems. Dynamic partial reconfiguration technology (DPR) is used to reduce FPGA resources and power consumption on chips. This paper proposes a model for high-speed Multiple-IPSec security systems that meet real-time applications. The system throughput, power consumption, and resources used when applying Multiple-Core and DPR architectures are also calculated.