Appendix A5: Programming a Finite State Machine

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Abstract

I was once asked by some of my students whether it was possible for software to run without hardware. This was an interesting question, and given that I spend much of my time writing computer programs, I felt well placed to answer it. First, I decided to look into the basic needs of software. The idea was to look at digital hardware and consider what basic hardware would be needed to produce a programmable system to make a finite state machine (FSM) that could be programmed to produce clock‐driven FSMs. It should be possible to use similar ideas for event‐driven FSM, but I have not looked into these yet. On reflection, it should be possible to program an FPGA with event cells that could be used with other hardware to make a programmable device. At first I looked at basic information available in some electronic digital devices, such as parallel loading counters, digital multiplexers, and quad latches, and eventually came up with the arrangement in Figure A5.1 for a programmable FSM. The system needs to be able to digitally count, so it makes use of a four‐stage clocked synchronous up counter. There is a need to be able to both increment the counter while also allowing the system to branch between states, so the counter needs to have parallel loading inputs so as to branch to these other states.
附录A5:有限状态机编程
有一次,我的一些学生问我,软件有没有可能在没有硬件的情况下运行。这是一个有趣的问题,考虑到我花了很多时间编写计算机程序,我觉得自己很适合回答这个问题。首先,我决定研究软件的基本需求。我们的想法是研究数字硬件,并考虑需要哪些基本硬件来生产一个可编程系统来制造一个有限状态机(FSM),这个有限状态机可以被编程来生产时钟驱动的FSM。对于事件驱动的FSM应该可以使用类似的想法,但我还没有研究过这些。经过反思,应该可以用事件单元对FPGA进行编程,这些事件单元可以与其他硬件一起使用,以制作可编程设备。首先,我查看了一些电子数字设备中可用的基本信息,例如并行加载计数器、数字多路复用器和四轴锁存器,并最终提出了图A5.1中可编程FSM的安排。该系统需要能够进行数字计数,因此它使用了一个四级时钟同步上行计数器。需要能够增加计数器,同时也允许系统在状态之间进行分支,因此计数器需要具有并行加载输入,以便分支到这些其他状态。
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