Adaptive Sub-Threshold Test Circuit

Abstract

Emerging ubiquitous systems such as distributed sensor networks require ultra-low power consumption. The energy minimum and thus, the lowest possible power consumption of CMOS logic, is achieved in the sub-threshold region. The exponential dependence of the drain current on threshold voltage variations leads to increased overdesign if sub-threshold circuits are to be robust. Adaptive systems are required to address variability robustness. One approach to achieve adaptivity is timing error detection (TED) within the circuit. Presented here is a TED latch capable of sub-threshold operation. It was designed in 65 nm technology, has an operating voltage range of 0.25 V through 1.2 V, and a minimum energy point (MEP) of 0.4 V. At the MEP, the average power consumption for one clock period and an activity factor of alpha=0.5 is 0.43 nW. The area of the TED latch is 101 um^2. A sub-threshold CORDIC implementation is presented to demonstrate the TED latch at a system level.