Suppression of self-excited oscillation for common package of Si-IGBT and SiC-MOS

Abstract

We propose a method to design a module structure avoiding the risk of self-excited (SE) oscillation. By simplifying both the semiconductor device and lumped circuit model, oscillatory conditions can be extracted analytically. Results show good agreement with T-CAD simulation and measurement results of test modules. The method is applied to the design of next generation common package, which has realized very low system inductance. SE oscillation can be prevented for latest generation Si-IGBTs having very small feedback capacitance and SiC-MOS having high output capacitance mounted in the same common package design.