DualStack: A High Efficient Dynamic Page Scheduling Scheme in Hybrid Main Memory

Abstract

With the development of big data and multi-core processors technology, DRAM-only based main memory cannot satisfy the requirements of in-memory computing in high memory capacity and low energy consumption. The emerging memory technology-phase change memory (PCM) is proposed to break the bottleneck of the current memory system. However, its weaknesses in write endurance and long access latency make it cannot fully replace DRAM. Consequently, researchers presented the architectural design aimed at DRAM/ PCM hybrids and the corresponding page migration scheme to give full play to their merits. The urgent challenges facing by existed page migration schemes are poor performed under weak locality in data streams and further improvement need in prediction of future access tendency. In this paper, we propose an efficient page migration policy called DualStack which features dynamic page management according to global read and write information and temporal locality. It is designed to keep write-intensive pages to DRAM and read-intensive pages to PCM, and specially avoid frequent and unnecessary migration between hybrid memory media. Compared to the state-of-the-art of hybrid main memory, our experimental results indicate that DualStack can effectively improve the system I/O latency by 38%~58% on the premise of reducing the system power consumption by 20%~30%.