{"title":"Test system of the time-over-threshold based chip optimized for linear transfer characteristics and low power for particle tracking applications","authors":"K. Kasinski, R. Kleczek","doi":"10.1109/MIXDES.2015.7208549","DOIUrl":null,"url":null,"abstract":"This paper presents the circuits and systems developed for testing the DSToTIC3 ASIC. Detailed study of the estimated noise performance in the presence of realistic external components is also a subject of this paper. DSToTIC3 is a prototype, 8-channel front-end electronics designed for the regime of long silicon strip sensors and interconnects of new tracking detectors. Layout and general architecture of the die is presented. Built-in digital-to-analog converters minimize the number of external components required for the chip operation, which makes it easily scalable to a final multichannel design.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2015.7208549","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the circuits and systems developed for testing the DSToTIC3 ASIC. Detailed study of the estimated noise performance in the presence of realistic external components is also a subject of this paper. DSToTIC3 is a prototype, 8-channel front-end electronics designed for the regime of long silicon strip sensors and interconnects of new tracking detectors. Layout and general architecture of the die is presented. Built-in digital-to-analog converters minimize the number of external components required for the chip operation, which makes it easily scalable to a final multichannel design.