Design of All-Digital Phase Locked Loop for Improved Frequency Lock Range

Abstract

This paper presents the design and implementation of All Digital Phase Locked Loop (ADPLL) for improved lock range. FPGA implementation of improvised ADPLL is carried out on Xilinx Artix-7(xc7alStcpg236-1) chip. The modified work is carried out for 200 KHz central frequency(fo) under complete digitalization. It provides a frequency lock range of 177 KHz to 222 KHz with Lock time of 12.57us and power consumption 0.088W under delay of 0.8 ns. This modified design, outputs an increase in Operational frequency range compared to previous design under low frequency.