Voltage regulator module (VRM) transient modeling and analysis

Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370) Pub Date : 1999-10-03 DOI:10.1109/IAS.1999.805965

P. Wong, F. Lee, Xunwei Zhou, Jiabin Chen

引用次数: 33

Abstract

In this paper, the transient response of the voltage regulator module (VRM) output voltage when the processor has a sudden load change is analyzed. The parasitic parameters play important roles in the transient. The system can be divided into several resonant loops. Each loop can be considered approximately as a decoupled second order system. The voltage drop of the capacitor is analyzed. By reducing the inductance and increasing converter bandwidth, the transient of VRM can be improved.

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稳压模块(VRM)暂态建模与分析

本文分析了处理器负载突然变化时稳压模块(VRM)输出电压的瞬态响应。寄生参数在瞬态过程中起着重要的作用。该系统可分为几个谐振回路。每个回路可以近似地看作是一个解耦的二阶系统。对电容器的压降进行了分析。通过减小电感和增大变换器带宽，可以改善VRM的暂态。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370)

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