Using power consumption in the performability of Fault-Tolerant FPGAs

Abstract

Over the last decade, several Fault-Tolerant techniques for FPGAs were proposed especially for recovering from permanent faults. Most of those techniques were based on relocation of the defective module into a new location acting as a spare. Accordingly, what is the suitable number of spares that should be added to a system? In this paper, a performability model is developed to quantitatively investigate the appropriate number of spares The model uses power consumption as the penalty. An example with three Markov models is studied to show system designers how to find the appropriate tradeoff between increase in reliability and decrease in performability.