Limits to neural computations in digital arrays

Abstract

In this paper the properties of artificial neural network computations by digital VLSI systems are discussed. We also comment on artificial computational models, learning algorithms, and digital implementations of ANNs in general. The analysis applies to regular arrays or processing elements performing binary integer arithmetic at various bit precisions. Computation rates are limited by power dissipation which is dependent upon required precision and packaging constraints such as pinout. They also depend strongly on the minimum feature size of the CMOS technology. We emphasize custom digital implementations with low bit precision, because these circuits require reduced power and silicon area. One way this may be achieved is using stochastic arithmetic, with pseudorandom number generation based on cellular automata circuits.