Performance Comparison of Explicit Pulsed Flip-Flops in Low Power and High-Speed Applications

Abstract

This paper presents a comparative study in the performance of three pulse flip-flops (P-FFs) designs with an explicit pulse generation structure. It includes explicit pulse triggered data close to output flip-flop (ep-DCOFF), the conditional discharging flip-flop (CDFF) and signal feed-through flip-flop (SFTFF). The Conditional discharging technique is incorporated in CDFF. This flip-flop is having the advantages of reduced internal switching activities, fewer glitches at the output, negative setup time and small input-to-output delay features. The SFTFF is having a signal feed-through mechanism due to its true single phase clock latch based structure. The SFTFF reduces the problem of longest discharge path exists in other conservative flip-flops with the explicit style of pulse production. This design features a better performance in speed and power. The performance of P-FF compared using cadence software in CMOS 90nm technology. The post-layout simulation result shows that SFTFF outperforms ep-DCOFF and CDFF by 36.8% and 23.4% in power consumption respectively. The SFTFF is having the advantage of 22.4% and 48.2% in Data-to-Q delay when compared with ep-DCOFF and CDFF respectively.