Implementation of AES algorithm on FPGA for low area consumption

Abstract

An AES algorithm can be implemented in software or hardware but hardware implementation is more suitable for high speed applications in real time. AES is most secure security algorithm to maintain safety and reliability of data transmission. The main goal of paper is AES hardware implementation to achieve less area and low power consumption which maintain standard throughput of data, also to achieve high speed data processing and reduce time for key generating. AES hardware implementation can easily reset and immediately erase data on disk. The conventional Sbox combinational logic is replaced by BRAM which gives instantaneous output. The AES 128/196/256 is implements on a FPGA using HDL language with help of Xilinx ISE tool.