Efficient Digital Implementation of n-mode Tensor-Matrix Multiplication

Abstract

With the growth of pervasive electronics, the availability of compact digital circuitry for the support of data processing is becoming a key requirement. This paper tackles the design of a digital architecture supporting the $n -$mode tensormatrix product in fixed point representation. The design aims to minimize the resources occupancy, targeting low cost and low power devices. Tests on a Kintex-7 FPGA confirm that the architecture leads to an efficient digital implementation, which can afford real-time performances on benchmark applications with power consumption lower than 100mW.