An all-digital adaptive approach to combat aging effects in clock networks

Abstract

In this paper, we analyze the impact of asymmetrical aging due to Bias Temperature Instability (BTI) in the clock tree segments of power efficient designs. The nonuniform aging of launch and capture clock segments could not only violate the setup timing but also result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths' timing adversely. We present a reference-less alldigital technique to detect the aging effects and measure quantitatively the extent of pulse-width-distortion. The measurement results are then applied to rectify the pulse width distortion such that the clock network output is restored to a 50-50 duty cycle. The technique is validated using SPICE simulation based on 45nm industry standard library. A resolution of sub-1ps is achievable for both distortion measurement and correction circuits.