A 32 Kbs on-chip memory with high port-multiplicity (5 reads and 2 writes) for effective implementation of shared memory systems

Abstract

In this paper, we discuss the design of a multi-port SRAM which is an essential component in a shared memory system. Proposed is an area efficient memory cell structure which is better in cell stability and more immune to cross-talk noise. Some special circuit techniques are employed in order to accommodate the high capacity (32 Kbs) and the high number of ports (5R and 2W) required by the application. The 7-port memory is implemented in a 0.25 /spl mu/m CMOS technology. Analyses prove that 200 MHz high speed operation, low peak power and complex read-write access functionality are achieved. The authors also show that such a design can be easily extended and adapted to other shared memory systems.