Pre-silicon Memory Validation

Abstract

For memory design, it will go through a series of quality assurance checks to validate the completeness of the collaterals before releasing to production usage. The quality check for memory collateral is similar to the quality check done within standard cell collaterals. The issue with memory collateral validation is the IP coverage, as memory instantiation is manual, unlike standard cell instantiation is handled by the EDA tool automatically. Hence, for memory design, the permutation of memory cells instantiation, the permutation of placement within the same type of memory IP and across memory IP types as well as exhaustive coverage of memory collateral from timing, layout, noise, functional model and reliability model are always the question unanswered, prior production release. Prior production release of memory collateral, limited memory instantiation is done based on design instantiation, such as application processing unit (APU) design blocks, digital signal processing (DSP) design block, graphic processing unit (GPU) design blocks as well as central processing unit (CPU) design blocks. For other hardmacro IPs such as GPIO or SERDES, the IP coverage is not a concern as the IP variant is limited. This paper will share the general-purpose memory design for the memory compiler’s pre-silicon validation that addresses the above concerns. Hopefully, the sharing will benefit the design community.