Optimized FPGA Realization of Digital Matched Filter in Spread Spectrum Communication Systems

Abstract

Digital matched filter (DMF) is the key component of fast pseudo noise (PN) code synchronization in direct spread-spectrum systems (DSSS), and its realization is a crucial technology of digital DSSP receiver. For long PN code DMF needs a mass of hardware resource, recursive delay chain, folded DMF and time-division multiplexing are used to optimize FPGA realization of DMF to reduce the consumption of FPGA resource, which would reduce the cubage and cost of the receivers'.