Global False Coupling Interaction-Aware Hierarchical Timing Analysis

Abstract

Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. A hierarchical design is unavoidable because of a huge circuit size. It is more important how we can consider hierarchically meaningful structure in circuit delay analysis. To improve accuracy of hierarchical timing analysis, in this paper we inject the notions of local false coupling interaction and global false coupling interaction, then propose a comprehensive approach that uses functional relations considering global false coupling interactions generated by connections between modules to identify valid coupling interaction. We present results on several benchmark circuits that show the value of considering the global false coupling interaction to reduce excessive conservatism during hierarchical timing analysis