An Area-Efficient Hardware Implementation for Real-Time Window-Based Image Filtering

Abstract

Real-time image processing is used in a wide range of vision applications in recent years. Whereas these processing require very high speed and computational power, hardware implementation is a good choice for achieving high performance. In this paper a new low capacity and parallel architecture based on a special memory management and arithmetic unit is proposed for real-time spatial image processing. The architecture is implemented on FPGA at a 50 MHz clock frequency and a processing time of 5 ms for 3 times 3 generic window-based operations on 512 times 512 gray-scale images. Experimental results show that the proposed architecture outperforms the existing architectures in the area utilization aspect.