R. Giofré, F. Costanzo, M. Sotgia, M. Cirillo, E. Limiti
{"title":"A GaN MMIC HPA with 50W Output Power and 50% PAE for S-Band Radar Systems","authors":"R. Giofré, F. Costanzo, M. Sotgia, M. Cirillo, E. Limiti","doi":"10.23919/EuMIC.2019.8909589","DOIUrl":null,"url":null,"abstract":"This paper presents the experimental results of a monolithic microwave integrated circuit (MMIC) high power amplifier (HPA) in Gallium Nitride (GaN) technology conceived for S-Band active electronically scanned array systems. The MMIC is based on a three-stage architecture and it is realized in a commercially available $0.25 \\mu m$ GaN process. The HPA provides an output power higher than 50W with an associated gain and a power added efficiency greater than 34dB and 50%, respectively, in a fractional bandwidth larger than 15%. The overall chip area is limited to 6x5.4 mm2.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EuMIC.2019.8909589","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents the experimental results of a monolithic microwave integrated circuit (MMIC) high power amplifier (HPA) in Gallium Nitride (GaN) technology conceived for S-Band active electronically scanned array systems. The MMIC is based on a three-stage architecture and it is realized in a commercially available $0.25 \mu m$ GaN process. The HPA provides an output power higher than 50W with an associated gain and a power added efficiency greater than 34dB and 50%, respectively, in a fractional bandwidth larger than 15%. The overall chip area is limited to 6x5.4 mm2.