Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer

S. Lim, M. Ding, Dexter Velez Sorono, Daniel Ismael Cereno, Jong-Kai Lin, V. S. Rao
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引用次数: 5

Abstract

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.
TSV衬垫上2.5D细间距铜柱凸接的热压粘合
智能手机和平板电脑等便携式电子设备的使用导致了对更多功能、更小尺寸和更低功耗要求的高需求。为了应对这些挑战,电子封装设计采用更薄的芯片和精细的间距碰撞。通过硅通孔(TSV)的2.5D和3D IC封装正在积极发展。在2.5D和3D IC系统中,更紧密的互连以及电路密度的增加提供了更高的性能和更低的功耗[1]。此外,由于硅节点较低、芯片尺寸减小和TSV技术,对细间距铜柱碰撞的需求也有所增加。在2.5D和3DIC集成中,为了满足电气连续性和高性能的要求,需要细间距互连。在现有的互连方法中,焊料微凸点因其材料成本和工艺成本低而备受关注[2]。铜柱FC键合工艺与传统FC键合工艺的主要区别在于减小了每个焊点上的焊料体积。因此,在焊料回流过程中,焊料没有自对准的优势。为保证良好的焊点形成,需要具有精确贴片能力的倒装片键合机。对于直径大于100 μm、间距大于150μm的较大凸点,仍然适用常规回流法[3]。焊点成型后可进行毛细填充(CUF)和模压填充(MUF)等后填充工艺。另一方面,当凸点的间距和/或FC的厚度进一步减小时,采用TC工艺结合铜柱凸点的FC将是小间距FC应用的解决方案之一。实验结果表明,凹凸间距可以减小到50 μm(直线间距)。这一过程也允许更好地控制焊料挤出的效果。然而,这个过程需要严格控制(i) FC和键合基板之间的平面化和(ii)每个焊点的隔离。必须建立良好的工艺参数,以确保没有焊料坍塌或打开接头。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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