Microarchitecture and performance analysis of a SPARC-V9 microprocessor for enterprise server systems

The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. Pub Date : 2003-02-08 DOI:10.1109/HPCA.2003.1183533

M. Sakamoto, A. Katsuno, Aiichiro Inoue, T. Asakawa, H. Ueno, K. Morita, Yasunori Kimura

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引用次数: 16

Abstract

We developed a 1.3-GHz SPARC-V9 processor: the SPARC64 V. This processor is designed to address requirements for enterprise servers and high-performance computing. Processing speed under multiuser interactive workloads is very sensitive to system balance because of the large number of memory requests included. From many years of experience with such workloads in mainframe system developments, we give importance to design a well-balanced communication structure. To accomplish this task, a system-level performance study must begin at an early please. Therefore we developed a performance model, which consists of a detailed processor model and detailed memory model, before hardware design was started. We updated it continuously. Once a logic simulator became available, we used it to verify the performance model for improving its accuracy. The model quite effectively enabled us to achieve performance goals and finish development quickly. This paper describes the SPARC64 V microarchitecture and performance analyses for hardware design.

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用于企业服务器系统的SPARC-V9微处理器的微体系结构和性能分析

我们开发了一个1.3 ghz的SPARC-V9处理器:sparc64v。该处理器旨在满足企业服务器和高性能计算的需求。多用户交互工作负载下的处理速度对系统平衡非常敏感，因为包含大量内存请求。根据多年来在大型机系统开发中处理此类工作负载的经验，我们认为设计一个平衡良好的通信结构非常重要。为了完成这项任务，系统级性能研究必须尽早开始。因此，在硬件设计开始之前，我们建立了一个性能模型，该模型由详细的处理器模型和详细的内存模型组成。我们不断更新。一旦逻辑模拟器可用，我们就使用它来验证性能模型，以提高其准确性。该模型非常有效地使我们能够实现性能目标并快速完成开发。本文介绍了sparc64v的微体系结构和硬件设计的性能分析。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.

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