Low-phase-noise eight-phase VCO using bottom series coupling technique

M. Wei, R. Negra, Sheng-Fuh Chang, Yen-Huang Hsu
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引用次数: 1

Abstract

This paper presents an eight-phase low-phase-noise VCO using series coupling technique, which obtains less phase error compared to the parallel coupling. Furthermore, the bottom-series coupling is used to achieve better phase noise than the top-series coupling. To properly design the complementary cross-coupling pair, the impedance locus theory is adopted. The chip is implemented in 180 nm CMOS technonlogy and has a chip area of 1.88 mm2. Measured oscillation frequency is from 1.51 GHz to 1.99 GHz (27.4 %). Measured minimum phase noise is −129.23 dBc/Hz at 1MHz offset at 1.51GHz leading to a FOMt of −189.0. The measured worst phase deviation is less than ±3.6° and the core power dissipation is 18mW from a supply voltage of 1.8 V.
采用底部串联耦合技术的低相位噪声八相压控振荡器
本文提出了一种采用串联耦合技术的八相低相位噪声压控振荡器,与并联耦合相比,其相位误差更小。此外,采用底串联耦合可以获得比顶串联耦合更好的相位噪声。为了合理设计互补交叉耦合副,采用了阻抗轨迹理论。该芯片采用180nm CMOS技术,芯片面积为1.88 mm2。测量振荡频率为1.51 GHz ~ 1.99 GHz(27.4%)。在1.51GHz的1MHz偏置下,测量到的最小相位噪声为−129.23 dBc/Hz,导致fof为−189.0。在供电电压为1.8 V时,测量到的最坏相位偏差小于±3.6°,铁芯功耗为18mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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