Buffer Reduction for Congestion Control during Timing Optimization

Abstract

In very-large-scale-integrated (VLSI) circuit design, Performance, Power and Area (PPA) are three very important indicators. Especially in the process of power-related chip design, possible trade-offs between these three indicators must be considered. In this work, we have developed two algorithms, respectively applying the greedy algorithm and the tree dynamic programming algorithm for redundant buffer reduction, in order to solve the local congestion problem of the chip. Redundant hold buffers are found and deleted during the timing optimization iteration, without making timing results worse. Through this method, the local cell area is reduced by 9.1%. It leaves room for other timing optimization, and reduces local utilization, routing congestion and short circuits.