FPGA based Power-Efficient Convolutional Neural Network

Abstract

Research into GPU (Graphics Processing Unit) acceleration using programmable logic arrays has mostly focused on Convolutional Neural Networks. These studies demonstrate the effectiveness of CNNs in various technical vision tasks, such as feature extraction, image analysis, face identification, and rear cross-traffic alert, amongst many others. As a result, there are restrictions on the times in which the CNN model can be implemented on FPGA, such as the restrictions on the quantity of on-chip memory, the dimensions of the CNN, and the parameters of the model. This work suggests a television commercial and an advanced CNN prototype informed by the basic AlexNet prototype. The proposed architecture uses a Commercial engine, an improved version of the insight separates, and a distinct permutation unit. In addition, the designers provide a GPU integration model that supports the Mish and Rectified linear initiation characteristics. The suggested method has a comparatively high detection accuracy while consuming a relatively little amount of the computer system's resources in contrast to other methods considered to be state-of-the-art. This proposed system is design in RTL Verilog Hardware description language. The proposed system is implemented in Xilinx ISE Design Suite-13.1 for use on Spartan -6 (Target Device). The synthesis tool optimized speed, area, and power.