A CMOS analog vector quantizer for pattern recognition

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824041

Y. Hung, Bin-Da Liu

引用次数: 3

Abstract

A linear mean-absolute-difference (MAD) cell is designed. Based on this cell and winner-take-all circuit, we propose a parallel analog vector-quantizer for pattern recognition. The experimental circuit is constituted by one input pattern and 16 template patterns with 16 elements. This circuit had been simulated using 0.5 /spl mu/m CMOS technology by HSPICE. The results show that a pattern can be correctly identified if the difference of the MAD distance metric is larger or smaller than 100 mV. Simulation results demonstrate 250 ns identified time and 16 mW power dissipation for single 3.3 V voltage supply.

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用于模式识别的CMOS模拟矢量量化器

设计了一种线性平均绝对差分(MAD)单元。基于该单元和赢者通吃电路，我们提出了一种用于模式识别的并行模拟矢量量化器。实验电路由一个输入模式和16个模板模式组成，包含16个元件。利用HSPICE软件采用0.5 /spl μ m CMOS技术对该电路进行了仿真。结果表明，当MAD距离度量的差值大于或小于100 mV时，可以正确识别出一种模式。仿真结果表明，单个3.3 V电压电源的识别时间为250 ns，功耗为16 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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