Low stress die attach material challenges for critical Si node with Cu wire

Megan Chang, Anderson Li
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引用次数: 5

Abstract

Low stress die attach material is of big interest for multi applications, for example, automotive, high voltage and thermal enhancement packages that require high package reliability performance; and sensitive output current applications for display driver, battery controller. The challenges of low stress die attach material started to occur when moving wire bonding technology from Au wire to Cu wire on specific Si nodes. Although it's well known that Cu wire bonding remains a challenge on bondpad with critical pad metallization or layout due to its harder wire property, however the fact that non-stick on bond pad tendency to occur on specific die attach materials with limited Si node combination became the challenge for moving forward the low stress package to low cost solutions. This paper includes the deep dive root causes investigation on the factors of die attach materials, Si nodes, and Cu wire bonding for the non-stick on pad failure. Design of experiment is carried considering materials, machines, methods include bond pad hillock, bond pad metallization thickness, wafer batch, die attach material batch, die attach material types, die attach outgas, die attach fillet height, bond line thickness, die tile, Cu wire bond jig...etc. The DOE results revealed the non-stick on pad root cause is a combination factors of die attach materials modulus at high bonding temperature, Si node under layer material types. Bond pad metallization thickness, die attach outgas, bond pad hillock... were not root cause of the bondability issue. Being the facts that Si node changed is high risk and also high cost, the solutions to overcome the non-stick on pad are mainly focus on die attach materials modulus and wire bonding technology enhancement. In this paper, we demonstrated the development of the reasonable modulus level for die attach materials to overcome the non-stick on pad issue for the sensitive Si nodes with Cu wire bonding. Besides, potential root causes are well studied via design of experiences. In the meantime, package reliability performance is well maintained post preconditioning, and stress treatment of temperature cycling per package requirement. With this study, we identify the solutions for the balance of Assembly manufacturability and package reliability.
低应力模贴材料挑战的关键硅节点与铜线
低应力贴片材料是多种应用的大兴趣,例如,汽车,高压和热增强封装,需要高封装可靠性性能;灵敏输出电流应用于显示驱动器、电池控制器等。当在特定Si节点上从Au线到Cu线的线键合技术移动时,低应力模贴材料的挑战开始出现。虽然众所周知,由于铜丝的硬性质,对于具有关键焊盘金属化或布局的键合垫来说,铜丝键合仍然是一个挑战,然而,在硅节点组合有限的特定贴片材料上,键合垫上的不粘现象往往会发生,这一事实成为将低应力封装推向低成本解决方案的挑战。本文从模具附着材料、硅节点、铜丝粘接等方面深入探讨了造成焊盘不粘故障的根本原因。实验设计考虑材料、机器、方法,包括焊盘丘、焊盘金属化厚度、晶片批次、贴模材料批次、贴模材料类型、贴模出气量、贴模圆角高度、贴模线厚度、贴模瓦、铜丝搭接夹具等。DOE结果表明,焊盘不粘的根本原因是高键合温度下的贴片材料模量和硅节点下层材料类型的综合因素。焊盘金属化厚度、模具附着气、焊盘丘…都不是债券问题的根本原因。由于硅节点改变风险高、成本高,克服焊盘不粘的解决方案主要集中在贴片材料模量和焊丝键合技术的提高上。在本文中,我们展示了合理模量水平的发展,以克服与铜线结合的敏感硅节点在焊盘上不粘的问题。此外,潜在的根本原因也通过体验设计得到了很好的研究。同时,经过预处理和温度循环应力处理后,封装的可靠性性能得到很好的保持。通过本研究,我们找到了平衡装配可制造性和封装可靠性的解决方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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