Session T1B: Tutorial: SoC testing

Abstract

This tutorial covers fundamental concepts, recent developments and industry practices on SoC hierarchical and modular test flow. It has two sections: 1. Core-level test technologies: In this section, we will cover three important topics in core-level DFT and ATPG. a. Test quality. We will introduce cell-aware ATPG. Industrial case studies will be used to illustrate this new fault model's contributions to test quality. b. Test compressions. We will first review the basics of the test compression technologies, which include test stimuli compression and test responses compaction. In the test stimuli compression, we will focus on continuous-flowbased technology, such as Embedded Deterministic Test (EDT). For the test responses compaction, we will briefly introduce space compaction, time compaction and hybrid compaction. Low power compression technologies will also be reviewed. c. Test point insertion. In the good old days, test point was used to improve the test coverage. However, the new trend in test industry is to use the new test point insertion technologies to reduce the pattern count. 2. SoC-level test technologies: In this section, we will cover the following important topics in SoClevel Testing a. This section starts with a review on published core-based SoC hierarchical DFT methodologies and techniques such as TAM, wrapper, test scheduling, and diagnosis etc. b. Illustrate SoC modular test flow and technologies such as broadcasting compressed test stimuli to multiple identical and non-identical cores, channel scaling, and flexible test accessible channels to optimize SoC pin utilization and reduce total SoC test time. c. Pattern retargeting based hierarchical SoC test and diagnosis flow. Dynamic bandwidth management will be explained. It can take advantage of pattern retargeting flow and achieve higher SoC test time reduction. IEEE 1687 (IJTAG) applications in the SoC test flow. This new IEEE standard makes cores to be tested at SoC in a plug-and-play manner.