Process simulation of Junctionless transistor for low power applications

Abstract

This proposed Technique deals with the process simulation of a Junctionless transistor which will overcome the drawbacks faced by Fabrication engineers. It also compares the performance of both single gate and multigate Junctionless transistors. All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult fabrication challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors. The main focus of this project work is to analyze the transistor parameters without going for real time fabrication. The parameters ideal for a good device is obtained by changing them with certain values. Using this process simulation, the errors in the device fabrication can be reduced.