Swamy Jakkula, Jayaram Nakka, P. S. V. Kishore, J. Rajesh, Sukanta Halder
{"title":"A New Nine Level Switched Capacitor-based Inverter with Quadruple Boosting Ability","authors":"Swamy Jakkula, Jayaram Nakka, P. S. V. Kishore, J. Rajesh, Sukanta Halder","doi":"10.1109/TEECCON54414.2022.9854839","DOIUrl":null,"url":null,"abstract":"In this article, a novel nine-level inverter with quadruple boosting capability is proposed. The suggested topology is based on the switched capacitor approach and employs two capacitors, fourteen switches, and one DC source to provide nine output voltage levels. It features self-balancing of capacitor voltages and polarity is created inherently without the usage of H-bridge. For the creation of gate pulses, the level shifted pulse width modulation (LSPWM) scheme is employed, and voltage stress analysis is performed on all switches at each voltage level. Simulations based on MATLAB/Simulink are used to analyze and validate the proposed topology under various parametric changes.","PeriodicalId":251455,"journal":{"name":"2022 Trends in Electrical, Electronics, Computer Engineering Conference (TEECCON)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Trends in Electrical, Electronics, Computer Engineering Conference (TEECCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEECCON54414.2022.9854839","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this article, a novel nine-level inverter with quadruple boosting capability is proposed. The suggested topology is based on the switched capacitor approach and employs two capacitors, fourteen switches, and one DC source to provide nine output voltage levels. It features self-balancing of capacitor voltages and polarity is created inherently without the usage of H-bridge. For the creation of gate pulses, the level shifted pulse width modulation (LSPWM) scheme is employed, and voltage stress analysis is performed on all switches at each voltage level. Simulations based on MATLAB/Simulink are used to analyze and validate the proposed topology under various parametric changes.