FPGA based decimator using fully parallel technique for hearing aid applications

Abstract

In this paper, implementation of a decimator using fully parallel technique for hearing aid applications is considered. A hearing aid is helpful for the people having hearing loss to hear more precisely in both quiet and whirring situations. It helps a person with hearing loss to listen and communicate by making sounds audible and clearer. The technique employed for the design of the filter is Canonic Signed Digit (CSD) representation. The higher sampling rate of the signal is decimated to low sampling rate by implementing the filter using the multirate approach. The main aim of the paper is to analyze and simulate the decimation filter using MATLAB. It is then simulated with ISE and finally implemented on FPGA devices. The two FPGA devices used are Spartan-3E and Virtex 2Pro. The comparison is done on two filter structures, Direct-form FIR and Direct-Form Symmetric FIR, for hardware resource utilization and speed. The hardware result shows that the proposed decimation filter designed on Virtex 2P with Direct Form symmetric structure is 12.79% faster than that designed on Spartan3E. The designed FIR filter with symmetric structure designed on Virtex 2P displays effective utilization of area and better speed in comparison to the design with Direct-Form structure on Spartan-3E.