{"title":"STarS: a target switching algorithm for sequential test generation","authors":"M. A. Heap, W. A. Rogers, William B. Burns","doi":"10.1109/VTEST.1991.208160","DOIUrl":null,"url":null,"abstract":"The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"385 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<>