Design and simulation of enhanced 64-bit Vedic multiplier

Abstract

Immense growth in technology and ever-increasing computational complexities in image and signal processing algorithms requires robust and efficient hardware software co-design methodologies. Multiplication operation forms the core of such extensively used techniques like correlation, convolution filtering etc. and it is one of the major contributing factors for deteriorating the system performance in terms of latency and throughput. This paper presents a design and implementation framework of enhanced multiplier based on prehistoric “Indian Vedic mathematics sutras”. Presented architecture is based on Vedic multiplication. The computation of partial multiplication is performed in parallel manner and further added to generate the result. In this work, a module of single carry save adder for performance enhancement replaces multiple adders. The partial multiplication terms are accustomed by concatenation. The Proposed design is simulated and implemented using Xilinx ISE Design Suit 14.5. Comparative analysis demonstrates that our proposed architecture for multiplication produce better results even for higher bits in terms of speed.