A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs

Abstract

A tool for managing finite state machines was developed and presented in this paper. The tool uses an algorithm of serial decomposition to perform operations on these FSMs. With the help of these operations, reduction in size of the combinational part of the circuit can be achieved, leading to smaller memory requirements. The resulting FSM implemented using an FPGA is provided with concurrent error detection (CED). The presented tool offers the designer an opportunity to trade-off error detection efficiency and implementation cost.